This invention relates generally to programmable logic devices, and more particularly to a method and system for creating support packages for customized FPGA-based SoCs.
Programmable devices are a class of general-purpose integrated circuits that can be configured for a wide variety of applications. Such programmable devices have two basic versions, mask programmable devices, which are programmed only by a manufacturer, and field programmable devices, which are programmable by the end user. In addition, programmable devices can be further categorized as programmable memory devices or programmable logic devices. Programmable memory devices include programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electronically erasable programmable read only memory (EEPROM). Programmable logic devices include programmable logic array (PLA) devices, programmable array logic (PAL) devices, erasable programmable logic devices (EPLD) devices, and programmable gate arrays (PISA).
As chip capacity continues to increase significantly, the use of field programmable gate arrays (FPGAS) is quickly replacing the use of application specific integrated circuits (ASICs). An ASIC is a specialized integrated circuit that is designed for a particular application and can be implemented as a specialized microprocessor. Notably, an FPGA is a programmable logic device (PLD) that has an extremely high density of electronic gates as compared to an ASIC. This high gate density has contributed immensely to the popularity of FPGAs. Notably, FPGAs can be designed using a variety of architectures that can include user configurable input/output blocks (IOBs), and programmable logic blocks having configurable interconnects and switching capability.
The advancement of computer chip technology has also resulted in the development of embedded processors and controllers. An embedded processor or controller can be a microprocessor or microcontroller circuitry that has been integrated into an electronic device as opposed to being built as a standalone module or xe2x80x9cplugin card.xe2x80x9d Advancement of FPGA technology has led to the development of FPGA-based system-on-chips (SoC) including FPGA-based embedded processor system-on-chips. A SoC is a fully functional product having its electronic circuitry contained on a single chip. While a microprocessor chip requires ancillary hardware electronic components to process instructions, a SoC would include all required ancillary electronics. For example, a SoC for a cellular telephone can include a microprocessor, encoder, decoder, digital signal processor (DSP), RAM and ROM. It should be understood within contemplation of the present invention that an FPGA-Based SoC does not necessarily include a microprocessor or microcontroller. For example, a SoC for a cellular telephone could also include an encoder, decoder, digital signal processor (DSP), RAM and ROM that rely on an external microprocessor. It should also be understood herein that xe2x80x9cFPGA-based embedded processor SoCsxe2x80x9d are a specific subset of FPGA-based SoCs that would include their own processors.
In order for device manufacturers to develop FPGA-based SoCs or FPGA-based embedded processor SoCs, it is necessary for them to acquire intellectual property rights for system components and/or related technologies that are utilized to create the FPGA-based SoCs. These system components and/or technologies are called cores or Intellectual Property (IP) cores. An electronic file containing system component information can typically be used to represent the core. A device manufacturer will generally acquire several cores that are integrated to fabricate the SoC.
Notwithstanding advantages provided by using FPGA-based SoCs, the development of these SoCs can be very challenging. Although a vast proportion of cores are commercially available, a significantly greater proportion of cores are proprietary. Proprietary cores can be called customer specific cores. Commercially available cores can typically include standardized interfaces, which can provide interconnectivity between system components from various vendors. Customer specific cores can typically include proprietary interfaces that do not readily facilitate interconnectivity between system components from other vendors. For example, customer specific cores can be written in proprietary languages, which are completely different from standardized languages. Since customer specific cores do not readily facilitate interconnectivity with other vendor""s system components, integrating customer specific cores during customization of an FPGA-based SoC can be time consuming. This resulted in increased development cost and greater time-to-market. Integration of the cores can include simulating, modeling and debugging the integrated cores in an operating environment. Simulation and modeling can be a daunting task since it can take hours if not days to simulate a few milliseconds of real time operation. FPGA based embedded processor SoCs are being introduced into the market, but there are no solutions which allow users to customize the system, the hardware cores, and the associated software nor is there a system enabling a user to tradeoff between a function which is implemented in hardware (FPGA fabric) or software (running on the embedded processor). It would be desirable to have a method and system for better integrating cores during customization of FPGA-based SoCs. After a system is customized with cores for an FPGA-based SoC, a software interface to a circuit board is needed. Traditionally, a Board Support Package (BSP) provided this software interface to a fixed entity (the circuit board) and included a collection of libraries which isolated all hardware specific functionality from the software. In the case of an FPGA-based SoC, a more dynamic solution is needed since the FPGA-based SoC is a much more dynamic environment than the traditional circuit board. Thus, a need exists for a software framework that supports the dynamic nature of customized FPGA-based SoCs.
In a first aspect, the present invention can provide a method for customization of the software of an FPGA-based SoC. Subsequent to selecting a system component used for customizing the FPGA-based SoC, parameters can be used to configure the selected system component for use with the FPGA-based SOC. The parameters used to configure the selected system component can be propagated and used to configure peer system components. Notably, other parameters that are used to configure the peer system component can also be propagated and used to configure the selected system component. The parameters used to configure the peer system components can be propagated to subsequently selected system components that can be used to configure the FPGA-based SoC. The method further comprises the step of creating a software interface to the selected system component or components and, to the peer system components. Selection of the system components can also include the provision of an option for selecting a hardware implementation or a software implementation for customizing the FPGA-based SoC. Additionally, the step of selecting the system component can include selecting a system component from the group consisting of a hardware core and a software core.
In another aspect of the present invention, a method of generating a chip support package for a customized FPGA-based SoC can comprise the step of monitoring during initialization of the customized FPGA-based SoC for at least one system component and associated parameters among a plurality of system components used for customizing the customized FPGA-based SoC and the step of creating a software interface based on the system components and associated parameters monitored.
In yet another aspect of the present invention, a support package generator for an FPGA-based system-on-chip (SoC) comprises a software interface having access to a collection of software component libraries for supporting functions of a customized FPGA-based SoC and a self contained directory specifying directory locations for items selected from the group comprising an output of the support package generator, a chip support package template file, a software device driver file.
The support package generator can also include software interface that serves as a software interface to hardware functions selected from the group comprising hardware initialization, interrupt handling, interrupt generation, hardware clock management, hardware timer management, mapping of local and bus memory spaces, and memory sizing.